Figure 25 – The data bus switch from the host processor 

 

One of the other parts of the VMS that has not been mentioned is the data bus switch, which includes a pair of 74LS245 bi-directional buffers and another 74HC157 to switch the output enable (OE) and write enable (WE) from the host processor to the dual memory banks. Each 74HC245 takes one of the memory data busses and then combines them into one bi-direction input/output which is fed to the host processor. The direction of the bus traffic is controlled by the state of the output enable pin, making the switch seem like a single bank of memory.

It was necessary to use the 74HC245 buffers in this part of the VMS as traffic is bi-directional from the host processor data bus into the memory banks. To write to the memory, the AVR sets the data port for output and then sets the OE and WE pins accordingly. To read from the memory, the processor port is set as an input, and then data is read after a small delay to allow the turnaround cycle to complete. This bus turnaround cycle is necessary when switching an AVR from output to input in order to avoid a bogus data reading. At 20MHz, only 2 dead cycles (NOPs) are needed, so it’s not a lot of wasted time.


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